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ENGR 851 - Advanced Microprocessor Architectures - Spring 2009

Instructor: Seapahn Megerian, Ph.D.
San Francisco State University
School of Engineering
ENGR 851 course bulletin

Contact Info and Office Hours:

Email:	engr851 at seapahn.us
Office:	SCI 170A
Office hours:	Tuesdays after lecture and by appointment.

Time and Place

Lecture, Tuesday, 18:10-20:55, Thornton Hall 428

Textbook

Computer Architecture, 4th Edition, A Quantitative Approach
- By John L. Hennessy and David A. Patterson
- Morgan Kaufmann Title
- ISBN: 978-0-12-370490-0

Course Description:

Engr 851 provides an overview of advanced topics in microprocessor design and computer architectures. In addition to delving into a wide array of traditional processor design issues such as computation models, instruction sets, memory organization, pipelining, speculative and out of order execution, superscalar, VLIW, and EPIC, class discussions will often revolve around current challenges, trends, and hot topics from both industrial and academic domains. The goal of the course is to present in-depth discussions in historic and state of the art architectures, while at the same time encouraging the exploration of options in the coming generations of post-"Moore's Law" age of computer design. Highly parallelized and massively multi-core (with hundreds, thousands, and even larger number of cores), the evolution of large-scale flash memories, and the ever increasing density of complex systems-on-chip are some of the factors that demand fundamental changes in how computer architects have been approaching new design problems. Students are expected to have taken an undergraduate level computer architecture course. Prior knowledge of operating systems, parallel programming, and multi-threading will be very helpful but is not required.

Prerequisites

Engr 456 - Computer Systems
Engr 356 - Basic Computer Architecture
Operating systems knowledge recommended.
Background and relevant material will be reviewed as deemed necessary by the instructor.

Grading

10% - Class participation
40% - Midterm
50% - Final exam

Tentative Course Schedule:

1-27: Introductions and course overview
2-03: Background review; performance metrics
2-10: RISC, CISC, Stack Processors, ...; Performance and reliability calculations
2-17: Multithreading and parallel programming; Parallel algorithms
2-24: Pipelining and hazards
3-03: ILP, VLIW, Superscalar, and dynamic scheduling
3-10: Midterm review
3-17: Midterm
3-24: Spring Recess - No class
3-31: Cesar Chavez Day - No class
4-07: Multi-processing, multi-threading, multi-issue
4-14: Memory hierarchy, caching, and analysis
4-21: Memory continued, cache coherence
4-28: Branch prediction and speculation
5-05: TBD
5-12: Final exam review

The sections below will be regularly updated throughout the course so check back often!

Announcements

Instructions to run SimpleScalar in Cygwin
New: Midterm Topics
New: Sample Midterm Questions
Midterm will be in class on Tuesday March 17, 2009.
- Open notes
- Open laptops
- With the exception of the instructor, obviously NO communication with anything that can pass the Turing Test (i.e. a live human) during the test.
- I plan to answer questions in the first half of class on tuesday (as much time as is needed to answer questions) before the test.
- Test will probably take less than 1 hour.
Project for 2 week break: Use LPSOLVE to perform register renaming.
- Input line format: [dest][[[, src1], src2], src3]
- Sample input:
R1, R2, R3 R1, R2 R1 , R5 , R5, R6 , R5, R6, R7
- The first optional field is the destination register.
- The remaining fields are source registers (up to 3).
- You can assume the input program will have already been transformed to this format.
- You only need to output the renamed registers in the same format.
- More on this project to follow.
See the cache index/tag example from class here.