ENGR 851 - Advanced Microprocessor Architectures - Fall 2010
Instructor: Seapahn Megerian, Ph.D.
San Francisco State University
School of Engineering
ENGR 851 course bulletin
Contact Info and Office Hours:
Email: | engr851 at seapahn.us |
Office: | SCI 170A |
Office hours: | Mondays after lecture and by appointment. |
Time and Place
Lecture, Monday, 18:10-20:55, HSS 305
Textbook
- Computer Architecture, 4th Edition, A Quantitative Approach
- By John L. Hennessy and David A. Patterson
- Morgan Kaufmann Title
- ISBN: 978-0-12-370490-0
Course Description:
Engr 851 provides an overview of advanced topics in microprocessor design and computer architectures. In addition to delving into a wide array of traditional processor design issues such as computation models, instruction sets, memory organization, pipelining, speculative and out of order execution, superscalar, VLIW, and EPIC, class discussions will often revolve around current challenges, trends, and hot topics from both industrial and academic domains. The goal of the course is to present in-depth discussions in historic and state of the art architectures, while at the same time encouraging the exploration of options in the coming generations of post-"Moore's Law" age of computer design. Highly parallelized and massively multi-core (with hundreds, thousands, and even larger number of cores), the evolution of large-scale flash memories, and the ever increasing density of complex systems-on-chip are some of the factors that demand fundamental changes in how computer architects have been approaching new design problems. Students are expected to have taken an undergraduate level computer architecture course. Prior knowledge of operating systems, parallel programming, and multi-threading will be very helpful but is not required.
Prerequisites
- Engr 456 - Computer Systems
- Engr 356 - Basic Computer Architecture
- Operating systems knowledge recommended.
- Background and relevant material will be reviewed as deemed necessary by the instructor.
Grading
10% - Class participation
40% - Midterm
50% - Final exam
Tentative Course Schedule:
- 8-30: Introductions and course overview
- 9-06: Labor Day: No Class
- 9-13: Background review; performance metrics
- 9-20: RISC, CISC, Stack Processors, etc; Performance and reliability calculations
- 9-27: Multithreading and parallel programming; Parallel algorithms
- 10-04: Pipelining and hazards
- 10-11: ILP, VLIW, Superscalar, and register renaming
- 10-18: Superscalar continued - scheduling
- 10-25: Midterm review
- 11-01: Midterm (no class)
- 11-08: Memory hierarchy, caching, and analysis
- 11-15: Memory continued, cache coherence
- 11-22: Recess: No Class.
- 11-29: Virtual Memory
- 12-06: Virtual Memory continued, Midterm review
- 12-13: Final exam review and announcements
The sections below will be regularly updated throughout the course so check back often!
Announcements
- Lecture Notes: 9-13 Overview (thanks Sajna!)
- Lecture Notes: 9-20 Pipelining (thanks Harsh!)
- Lecture Notes: 9-27 Pipelining 2 (thanks Padam!)
- Instructions for installing SimpleScalar and GCC cross-compiler
- From the instructions, you'll need:
- Worked fine for 10.04 ubuntu 32-bit.
- For 10.04 ubuntu 64-bit:
- export $HOST=i686-unknown-linux
- sudo apt-get install libc6-dev-i386
- Alternate instructions for installing SimpleScalar and the cross compiler. (thanks to Nima!).
- See sample Midterm topics and sample pipelining question.
- Lecture Notes: 10-11 Register Renaming (thanks Timo!)
- Lecture Notes: 10-18 Scheduling (thanks Abhishek!)
- SimpleScalar installer script (thanks Liang!) Use at your own risk as I have not tested it myself. --Seapahn
- Midterm - Take Home - Emailed to class on 11-1-2010 at 6:00pm.
- I will be available to answer questions through email from 6-8pm.
- No class on Monday 11-1-2010
- Take-Home Midterm
- Due 11:59pm, Sunday Nov 7th.
- No class Monday 11-1-2010.
- Cache index/tag example from class here.
- Lecture Notes: 11-08 Cache Intro (thanks Eli!)
- Winner of the week by default!
- Lecture notes: 11-15 Caches continued.
- Lecture Notes: 11-29 Virtual Memory (thanks Sagar!)
- sim-cache example command line:
sim-cache -cache:dl1 dl1:256:32:2:l -cache:il1 dl1 -cache:il2 none -cache:dl2 none program_name
- L1 unified cache, 256 lines (sets), block size 32 (bytes), 2-way set associative, LRU replacement
- L1 instruction cache (il1) points to data cache (dl1)
- No L2 caches
- Final - Take Home
- Emailed to class on Tuesday 12-14-2010 at 6:00pm.
- Due 8:59pm, Monday Dec 20th.
- The Final Exam has been emailed to the class. If you did not receive it, please contact me.